Reconfigurable HSMs: Future Proofing Hardware Security

Reconfigurable HSMs: Future Proofing Hardware Security

Speakers: Pablo Trujillo

Conference: DEF CON

YouTube: https://www.youtube.com/watch?v=9slY1DllYhw

Overview

This talk, presented by Pablo Trujillo at DEF CON, addresses the critical need for robust and adaptable security mechanisms in an increasingly complex threat landscape. Trujillo, an FPGA designer, emphasizes the vulnerabilities of current cryptographic algorithms and hardware implementations, particularly in the face of emerging threats like quantum computing. The core proposition of his presentation is the adoption of reconfigurable devices, such as Field-Programmable Gate Arrays (FPGAs), as a superior alternative to traditional fixed-function hardware security modules (HSMs).

The presentation delves into the fundamentals of cryptographic hash functions and keys, detailing their evolution, common vulnerabilities, and the limitations of both software and conventional hardware implementations. Trujillo articulates how quantum algorithms like Grover's and Shor's pose an existential threat to widely used cryptographic primitives, potentially rendering much of our digital security infrastructure obsolete. By advocating for FPGAs, he outlines a pathway to future-proof hardware security, enabling the dynamic update and adaptation of cryptographic algorithms and architectures to counter novel attack vectors, including post-quantum threats and sophisticated side-channel attacks.

This topic is paramount for anyone involved in designing, deploying, or securing digital systems. As the quantum threat looms closer, understanding how to build resilient cryptographic foundations is no longer a theoretical exercise but an urgent practical necessity. Trujillo’s deep dive into FPGA capabilities for security offers a tangible and open-source-driven solution to a problem that demands proactive, hardware-level innovation.

Background

▶ Watch: Introduction: Quantum threats and reconfigurable security (0:00)

The foundation of modern digital security rests heavily on cryptographic algorithms and the secure management of keys. These "privacy protectors" are broadly categorized into hash algorithms and encryption keys.

Hash algorithms like MD5 and the SHA family (SHA-0, SHA-1, SHA-2, SHA-3) serve to generate a fixed-length output (a hash) from a variable-length input. A key property is that even a minor change in the input should produce a drastically different output, making them ideal for verifying data integrity. Historically, several hash algorithms have fallen victim to collision attacks, where attackers find two different inputs that produce the same hash. SHA-0, MD5, and SHA-1 have all been successfully broken this way. Currently, SHA-2 and SHA-3 are considered secure, but quantum computing poses a significant threat to SHA-2.

Encryption keys are essentially digital passwords used to encrypt and decrypt data. Two primary types exist: symmetric keys, where the same key is used for both encryption and decryption, and asymmetric keys, which use a public/private key pair. Asymmetric encryption solves the key distribution problem inherent in symmetric systems, as the public key can be freely shared to encrypt data, while only the holder of the private key can decrypt it. Common asymmetric algorithms include RSA and ECC, while AES is a widely used symmetric algorithm. The performance, or speed, of these algorithms is crucial, especially for real-time applications like TLS (Transport Layer Security) and SSH (Secure Shell).

Implementing these algorithms can be done in two main ways: software implementation and hardware implementation.

Software implementations involve writing code (e.g., C, Python) to perform the mathematical and logical operations. While flexible and easy to update, software approaches suffer from poor performance due to operating system overhead and the sequential nature of processor instruction execution. Manufacturers often address this by integrating processor extensions (e.g., SHA-NI for SHA, AES-NI for AES) which are dedicated hardware blocks near the CPU. However, software implementations still carry the risk of keys being stored insecurely on hard disks or in volatile RAM, and they introduce a dependency on specific processor architectures and extensions, limiting portability, especially in embedded systems.

Hardware implementations, on the other hand, use dedicated external devices to execute cryptographic algorithms. These offer superior performance, robust secure storage for keys (often read-only), and eliminate CPU dependency. However, they introduce a dependency on the specific hardware used and typically implement only widely standardized algorithms (e.g., SHA-256, AES-256). A prime example of such hardware is the Trusted Platform Module (TPM), a cryptographic processor usually integrated into motherboards. TPMs provide secure key storage and a suite of cryptographic functions, with TPM 2.0 being a requirement for modern operating systems like Windows 11. Despite their benefits, TPMs are generally fixed-function devices, raising concerns about their ability to adapt to future threats, a problem acknowledged even by the Trusted Computing Group, the developers of TPM 2.0.

The most significant looming threat to current cryptography is quantum computing. Unlike traditional bits that are either 0 or 1, quantum bits (qubits) can exist in a superposition of both states simultaneously due to quantum physics principles. This allows quantum processors to evaluate multiple choices concurrently. Two quantum algorithms are particularly menacing to cryptography:

1. Grover's Algorithm: This algorithm can speed up searches in unstructured databases. For cryptographic purposes, it effectively reduces the security strength of symmetric keys and hash functions. For instance, a 256-bit symmetric key could be broken with the equivalent effort of breaking a 128-bit key. SHA-256 and AES-128 are significantly weakened by Grover's algorithm.
2. Shor's Algorithm: This algorithm can efficiently find the prime factors of large integers. This directly breaks widely used asymmetric encryption schemes like RSA, which relies on the computational difficulty of factoring large numbers.

The practical impact of these algorithms is profound: RSA, SHA-256, and AES-128 are all rendered vulnerable. While SHA-3 appears to be more resilient, many existing hardware security solutions, such as certain Infineon TPMs, do not support post-quantum resistant algorithms or even stronger classical algorithms like SHA-512 or SHA-3, leaving them exposed to future quantum attacks. This inherent rigidity of fixed-function hardware underscores the need for a more adaptable security paradigm.

Key Findings

▶ Watch: Symmetric vs. Asymmetric Keys: Understanding the difference (4:00)

The central finding presented by Pablo Trujillo is that the current cryptographic landscape, underpinned by widely adopted algorithms like RSA, SHA-2, and AES-128, is fundamentally vulnerable to the advent of quantum computing. This vulnerability stems from the power of quantum algorithms like Grover's algorithm (which significantly reduces the effective key length for symmetric ciphers and hash functions) and Shor's algorithm (which can efficiently break public-key cryptography based on integer factorization, such as RSA).

Trujillo highlights that traditional hardware security modules (HSMs) and Trusted Platform Modules (TPMs), while offering benefits like secure key storage and hardware acceleration, suffer from a critical design flaw: their fixed-functionality. These devices are typically programmed during manufacturing with a specific set of widely used algorithms, making them rigid and incapable of adapting to new cryptographic standards or emerging threats, particularly the transition to Post-Quantum Cryptography (PQC). An illustrative example is shown with an Infineon TPM that lacks support for quantum-resistant algorithms or even stronger classical alternatives like SHA-3 or SHA-512, thus confirming its future vulnerability.

The key contribution and proposed solution is the advocacy for reconfigurable devices, primarily FPGAs, as the future of hardware security. Unlike fixed-function ASICs or processors, FPGAs allow their internal hardware architecture to be dynamically reconfigured, not just reprogrammed. This capability offers unprecedented resilience, enabling cryptographic algorithms to be updated, replaced, or modified post-deployment to counter new attacks or integrate PQC algorithms without requiring a complete hardware overhaul. This reconfigurability, combined with the inherent benefits of hardware acceleration and secure key storage, presents a robust, future-proof approach to securing critical digital assets against both classical and quantum threats.

Technical Deep Dive

▶ Watch: The critical role of algorithm performance in real-time security (5:45)

The core of Pablo Trujillo's proposed solution lies in the utilization of reconfigurable devices, specifically Field-Programmable Gate Arrays (FPGAs). Unlike traditional processors or ASICs (Application-Specific Integrated Circuits), FPGAs are integrated circuits whose internal hardware architecture can be reconfigured by the user or designer. This is distinct from mere "reprogrammability" in software; it means the actual logic gates and interconnections can be altered. This capability is pivotal for future-proofing security because it allows for the dynamic update of cryptographic algorithms and countermeasures directly at the hardware level.

An FPGA consists of a matrix of interconnected components:

• Configurable Logic Blocks (CLBs): These are the fundamental building blocks, containing look-up tables (LUTs) and flip-flops, used to implement arbitrary logic functions.
• Input/Output (I/O) Blocks: Interface with external devices.
• Dedicated Hardware Blocks: Such as multiplication and accumulation blocks (DSPs) for high-speed arithmetic operations, and Block RAM (BRAM) for on-chip memory.

The critical advantage of this architecture for cryptography is the ability to implement multiple, distinct cryptographic algorithms in different, isolated regions of the FPGA, allowing them to run in parallel. For instance, SHA-256 and RSA-2048 could operate concurrently on separate sections of the chip. If one algorithm (e.g., SHA-2) is later found to be vulnerable (e.g., due to quantum computing), only that specific portion of the FPGA's configuration needs to be updated. The vulnerable SHA-2 implementation could be replaced with a post-quantum cryptography (PQC) algorithm like SHA-3, or RSA with a lattice-based algorithm like Kyber, without affecting other functions or requiring a hardware replacement. This partial reconfiguration capability is a powerful feature.

FPGAs also offer significant advantages in mitigating side-channel attacks (SCAs). SCAs, such as timing attacks or power analysis attacks, infer sensitive information (like cryptographic keys) by observing the physical characteristics of a device during cryptographic operations. Because FPGA designs are implemented directly in hardware, designers have fine-grained control over circuit timing and resource allocation. Trujillo explains that an FPGA can be designed to ensure that cryptographic operations, regardless of the key or data being processed, always take the same amount of time. This uniform execution time effectively confuses timing attacks. Similarly, careful hardware design can mask power consumption variations, making power analysis more difficult.

Furthermore, FPGAs can be leveraged for True Random Number Generation (TRNG). The inherent physical properties of an FPGA, such as variations in silicon purity from manufacturing, local temperature fluctuations, and external pressure, introduce random delays in signal propagation between logic blocks. By carefully measuring and harnessing these uncontrolled delays, an FPGA can generate high-quality, non-deterministic random numbers crucial for cryptographic key generation and nonce creation.

Despite these advantages, FPGAs present some potential disadvantages that require specific mitigation strategies:

1. Volatility of Configuration Memory: Many FPGAs use RAM-based configuration memory, meaning the design is lost when power is removed. This typically necessitates an external non-volatile memory (e.g., a flash memory) to store the FPGA's configuration bitstream.

• Solution: Modern FPGAs, such as the AMD Spartan 7, offer built-in security features. The configuration bitstream can be encrypted with AES-256, and the decryption key is securely stored within the FPGA using fuses during the manufacturing process. These fuses are non-readable externally, preventing key extraction. Additionally, the JTAG interface, often used for debugging and programming, can be disabled post-deployment to prevent unauthorized reprogramming.

1. Lack of Internal Non-Volatile Memory for Keys: While the FPGA's configuration can be secured, the cryptographic keys themselves might need non-volatile storage.

• Solution: An external EEPROM (Electrically Erasable Programmable Read-Only Memory) can be added to the board. An SPI driver within the FPGA can then encrypt all data written to this EEPROM. Crucially, the encryption key for the EEPROM can also be stored in non-readable fuses inside the FPGA, making it write-only and highly secure.

1. Higher Power Consumption: FPGAs generally consume more power than fixed-function ASICs or TPMs due to their reconfigurable nature and the overhead of programmable interconnects. This is a design trade-off that needs to be considered for specific applications.

Trujillo's proof-of-concept design also highlights practical interface considerations. He opted for an SPI (Serial Peripheral Interface) over the more common I2C (Inter-Integrated Circuit) interface for his HSM. This choice was driven by the need for higher data throughput, with SPI capable of speeds up to 50 Megabits per second (Mbps), and potentially higher with interfaces like PCI. This speed is crucial for real-time ciphering applications, where cryptographic operations must keep pace with data streams (e.g., video feeds, high-bandwidth network traffic). The customizability of FPGAs allows for the creation of very specific, optimized solutions, as demonstrated by the example of a camera connected to a crypto module, with encrypted communication to a host via a high-speed SPI interface.

Demo / Proof of Concept

▶ Watch: Limitations and vulnerabilities of software-based security implementations (6:50)

As part of the talk, Pablo Trujillo presented a tangible Proof of Concept (PoC) in the form of an open-source Hardware Secure Module (HSM). This module is built around an AMD Spartan 7 FPGA, showcasing the practical application of reconfigurable hardware for cryptographic security.

The design is explicitly stated as open-source, emphasizing its accessibility for further development and scrutiny within the security community. A key architectural decision in this HSM was to deviate from the traditional I2C (Inter-Integrated Circuit) communication protocol, commonly found in many embedded and security devices. Instead, Trujillo's design utilizes a Serial Peripheral Interface (SPI). This shift was motivated by performance requirements, as the SPI interface can achieve speeds of up to 50 Megabits per second (Mbps) with the chosen device, significantly faster than typical I2C implementations. This higher throughput is critical for applications demanding real-time ciphering, where data must be encrypted and decrypted rapidly without introducing unacceptable latency. The speaker also noted that even higher speeds could be attained by employing more advanced interfaces like PCI.

A significant feature of this FPGA-based HSM is its capability for remote updates. Once the device is deployed in the field, its internal hardware configuration (i.e., the cryptographic algorithms implemented within the FPGA) can be updated remotely. This directly addresses the rigidity of fixed-function hardware, allowing the HSM to adapt to new cryptographic standards, patch vulnerabilities, or integrate post-quantum algorithms without requiring physical access or a complete hardware replacement.

Trujillo provided a simple yet illustrative use case for his custom solution: a camera connected to the FPGA-based crypto module. The communication between the camera and the crypto module is secured, and then the encrypted data is transmitted to a host system. On the host side, another identical crypto module decrypts the data, allowing the host to interact with the camera feed in a secure, high-speed manner (e.g., via the 50 Mbps SPI interface). This demonstration highlights the module's ability to provide end-to-end real-time cryptographic protection for data streams, tailored to specific application needs.

Defensive Implications

▶ Watch: Transition to hardware implementations for robust security (10:00)

The insights presented by Pablo Trujillo have profound implications for defensive security strategies, particularly in preparing for the quantum era and enhancing resilience against sophisticated attacks.

1. Prioritize Reconfigurable Hardware for HSMs: Organizations should actively evaluate and begin transitioning their critical cryptographic infrastructure from fixed-function HSMs (like older TPMs or ASICs) to reconfigurable hardware security modules, primarily those based on FPGAs. This proactive shift is essential to future-proof systems against emerging threats, especially quantum computing, by allowing dynamic updates to cryptographic algorithms and hardware architectures.
2. Develop a Post-Quantum Cryptography (PQC) Migration Strategy: The vulnerability of current algorithms (RSA, SHA-2, AES-128) to quantum attacks necessitates a clear PQC migration roadmap. FPGA-based HSMs are uniquely positioned to facilitate this transition, enabling the seamless integration and testing of new PQC algorithms (e.g., replacing RSA with Kyber or SHA-2 with SHA-3) without costly hardware replacements.
3. Strengthen Side-Channel Attack Mitigation: Defenders should leverage the fine-grained control offered by FPGAs to implement robust countermeasures against side-channel attacks. Designing hardware implementations that ensure constant execution time for cryptographic operations, irrespective of input data or key values, can significantly reduce the effectiveness of timing and power analysis attacks.
4. Enhance Key Management and Storage: The use of FPGA internal fuses for storing master encryption keys (e.g., for bitstream encryption or external memory encryption keys) provides a highly secure, non-readable storage mechanism. Organizations should adopt architectures that utilize these hardware-backed secrets, combined with encrypted external memory (e.g., EEPROM with SPI driver) for application-specific keys, ensuring keys remain protected even if the device is physically compromised.
5. Embrace True Random Number Generation (TRNG): Relying on hardware-derived TRNG, as enabled by FPGA's physical characteristics, is crucial for generating high-quality cryptographic keys, nonces, and other random values. This reduces reliance on potentially weaker pseudo-random number generators (PRNGs) and enhances overall cryptographic strength.
6. Consider Remote Update Capabilities: For deployed systems, the ability to remotely update the cryptographic hardware configuration is a game-changer. This allows for rapid response to newly discovered vulnerabilities or the deployment of PQC algorithms without requiring physical access, minimizing operational disruption and security exposure.
7. Customized Security Solutions: FPGAs enable the creation of highly customized security solutions tailored to specific application requirements and threat models. Instead of relying on generic, off-the-shelf security components, organizations can design unique cryptographic accelerators and security enclaves that are less susceptible to mass-market attacks.
8. Audit Existing Cryptographic Hardware: Conduct thorough audits of existing hardware security components to identify fixed-function devices that may not be adaptable to post-quantum standards or robust against advanced side-channel attacks. Prioritize replacement or upgrade plans for these vulnerable assets.

Key Takeaways

• Quantum Computing Threat is Real: Current mainstream cryptographic algorithms like RSA, SHA-2, and AES-128 are highly vulnerable to quantum attacks (Shor's and Grover's algorithms), necessitating a paradigm shift in hardware security.
• Fixed-Function Hardware is Insufficient: Traditional hardware security modules (HSMs) and TPMs, being fixed-function, cannot adapt to emerging threats or integrate post-quantum cryptography, leading to premature obsolescence and security gaps.
• Reconfigurable Hardware (FPGAs) is the Solution: FPGAs offer a flexible, future-proof approach by allowing dynamic updates and reconfigurations of their internal hardware, enabling seamless adoption of new cryptographic algorithms and countermeasures.
• Enhanced Security Capabilities: FPGA-based HSMs provide superior benefits, including parallel execution of multiple algorithms, robust side-channel attack mitigation, secure key storage using hardware fuses, and true random number generation.
• Practical & Deployable: The presented open-source FPGA-based HSM demonstrates a practical design with high-speed interfaces (SPI up to 50 Mbps) and remote update capabilities, proving the viability of this approach for real-world applications.
• Proactive PQC Adoption is Crucial: Organizations must proactively prepare for the post-quantum era by investing in adaptable hardware security solutions and developing strategies to migrate to quantum-resistant cryptographic algorithms.

About the Speaker(s)

Pablo Trujillo is a specialist in FPGA design, distinguishing himself from typical software developers in the security conference circuit. He is recognized for his contributions to the open-source community and his expertise in hardware implementation. Trujillo regularly shares his knowledge and projects online, writing for platforms such as Hackster and Hackaday, and maintaining his personal blog, contourpath.com. He is also active on Twitter under the handle @contropath.