Panel: Silicon Under Attack: Physical Exploitation of Modern Chips

Panel: Silicon Under Attack: Physical Exploitation of Modern Chips

Speakers: Lionel Riviere (Security Analyst, eShard); Joe Grand (Principal Engineer, Grand Idea Studio); Domenic Forte (University of Florida)

Conference: Hardwear.io USA

YouTube: https://www.youtube.com/watch?v=BsIIFvXxeh4

Overview

This Hardwear.io USA panel, "Silicon Under Attack: Physical Exploitation of Modern Chips," brought together leading experts Lionel Riviere, Joe Grand, and Domenic Forte to dissect the evolving landscape of physical attacks on silicon. The discussion pivoted on a critical observation: physical attacks are no longer the exclusive domain of state-sponsored actors or elite research labs. With tools becoming orders of magnitude cheaper and open-source frameworks readily available, "the bencher is real," signaling a significant democratization of these formidable attack vectors.

The panel explored a specific, highly relevant scenario: a modern automotive microcontroller, deployed in tens of millions of vehicles, holding critical keys for immobilizers, V2X communication, and ECU integrity. The core objective was to investigate three live attack paths across varying cost tiers and, crucially, to understand why none of them trigger any alarm on the target chip. Despite decades of defensive research into primitives like polymorphic circuits and self-destructive registers, these countermeasures are conspicuously absent from production silicon, highlighting a profound "deployment gap" that leaves many devices vulnerable.

The conversation delved into the practicalities and complexities of modern physical exploitation, from accessible bench-top setups to sophisticated lab environments. It also touched upon emerging challenges posed by advanced chip architectures like 3DIC and chiplets, the blurring lines between physical and software attacks, and the dual role of Artificial Intelligence as both a new target and a powerful accelerant for attackers. Ultimately, the panel confronted the pressing question of why cutting-edge defenses are not shipping, urging a re-evaluation of security priorities across the industry.

Background

▶ Watch: Introduction: Physical exploitation is cheaper, defenses are not shipping (0:00)

Physical attacks on integrated circuits, once considered esoteric research curiosities, have rapidly moved into the realm of practical threats. A significant driver of this shift is the dramatic reduction in the cost and accessibility of necessary tooling. As Joe Grand highlighted, equipment that once required a top-tier lab is now within the reach of hobbyists, with tools like ChipWhisperer, NewAE platforms, and even DIY EMFI (Electromagnetic Fault Injection) setups built on consumer-grade Amazon CNC router kits costing hundreds to a few thousand dollars. This democratization, coupled with open frameworks and online tutorials, has lowered the barrier to entry for aspiring hardware hackers.

Concurrently, academic and industry research has long addressed the theoretical aspects of defending against these attacks. Domenic Forte noted that defensive literature on topics such as polymorphic circuits, self-destructive registers, and voltage tamper detection has existed for over a decade. However, the critical disconnect lies in the lack of widespread adoption of these robust countermeasures in commercially available silicon. The panel's hypothetical scenario—a ubiquitous automotive microcontroller responsible for high-stakes functions like immobilizers and V2X—underscores this vulnerability, as such devices are routinely deployed without the advanced protections discussed in academic circles.

The underlying reasons for this persistent vulnerability are multi-faceted. Security often lags behind performance and cost optimization in chip design, especially with the rapid advancements in architectures like 3D Integration (3DIC) and chiplets. Manufacturers, facing intense market pressure, frequently prioritize features and time-to-market over comprehensive security. As Joe Grand revealed, some vendors are aware of known vulnerabilities in their chips but opt to upsell more expensive, "secure" microcontrollers rather than patching existing, widely deployed products. This commercial calculus, combined with a lack of concerted pressure from buyers, regulators, or even insurers, perpetuates a cycle where security remains an afterthought, creating the deployment gap that the panel sought to highlight.

Key Findings

▶ Watch: Lionel Riviere: High-end laser attacks and tooling evolution (7:00)

The panel discussion revealed several critical findings regarding the state of physical exploitation and defense:

• Democratization of Attack Tools: Physical attacks, particularly fault injection (voltage and electromagnetic), are no longer exclusive to well-funded labs. Tools like ChipWhisperer and ChipShouter are accessible for hundreds to a few thousand dollars, enabling individuals like Joe Grand to conduct sophisticated attacks using relatively low-cost setups, such as an Amazon CNC router kit for EMFI positioning. This significantly lowers the barrier to entry for hardware hacking.

• Evolving Attack Surface with Advanced Packaging: Modern chip architectures like 3DIC and chiplets significantly expand the attack surface. Domenic Forte explained that chiplets within the same package can potentially attack each other, and the closer proximity leads to a lower signal-to-noise ratio for eavesdropping or fault injection. While these advancements (e.g., Intel's Power Via technology) can introduce new attack vectors, they also present new physical barriers to traditional direct access, creating a dual-edged sword for both attackers and defenders.

• Impact of Lithography and Frequency on Attack Complexity: Lionel Riviere detailed how shrinking lithography (e.g., from 90nm to 14nm, 7nm, or 3nm) complicates precise laser fault injection. A 1 micrometer laser spot that might target a few transistors on older nodes can hit hundreds of thousands on newer, denser silicon, making repeatable, targeted faulting much harder. However, this increased complexity is not a countermeasure itself, merely an obstacle. Despite increasing device frequencies (tens of MHz to GHz), nanoscale laser systems remain effective for fault injection.

• Emergence of Remote Physical Exploitation: The panel discussed the blurring line between physical and software attacks. Concepts like software-induced physical attacks, Rowhammer-class effects, and remote glitching suggest a future where physical exploitation might not always require direct physical access. Joe Grand highlighted the potential for hardware implants to exfiltrate data or inject faults remotely, effectively turning a physical attack into a remote one once the implant is in place.

• AI as a Dual-Purpose Element:
• AI as a Target: Embedded AI inference models (specifically their weights) are emerging as new critical assets on a chip. Attacking these via side channels is more complex than traditional crypto attacks due to the "messy" and less predictable execution patterns, leading to a much lower signal-to-noise ratio for acquisition and analysis.
• AI as an Accelerant: AI tools, particularly Large Language Models (LLMs) and reinforcement learning, are proving invaluable for attackers. Lionel Riviere noted that AI can help build custom attack paths, while Joe Grand uses it for tasks like binary analysis (e.g., via Ghidra modules feeding into ChatGPT), plotting data, and generally saving hours of tedious work, thus allowing attackers to focus more on the core hacking process.

• The "Deployment Gap" in Defensive Measures: A central and concerning finding was the widespread absence of mature defensive primitives (like Domenic Forte's polymorphic registers) in production silicon. Despite their proven efficacy in research, cost-benefit analyses, lack of regulatory pressure, and a general industry inertia mean these defenses are not shipping. Manufacturers often prioritize selling more expensive "secure" versions rather than integrating robust security across their product lines.

Technical Deep Dive

▶ Watch: Remote physical attacks: blurring hardware/software boundaries (15:00)

The panel provided a comprehensive technical overview of physical exploitation techniques, the challenges posed by modern chip architectures, and the innovative defensive primitives being developed.

Fault Injection Methodologies:

Joe Grand initiated the discussion by describing his journey into fault injection. He began with voltage fault injection on targets like the Trezor Model 1 STM32 F2, aiming to replicate public work. While initially experiencing unreliable results, he transitioned to EMFI (Electromagnetic Fault Injection) using a ChipShouter on a custom platform built from an Amazon CNC router kit. This setup allowed for systematic XY scanning to characterize devices and campaign for fault injection, determining crashing versus non-crashing behavior. Joe emphasized the scientific process of logging and narrowing down conditions, highlighting that sometimes the exact mechanism of corruption isn't as important as achieving the desired outcome.

Lionel Riviere elaborated on the higher-end approach of laser fault injection employed by eShard. While the methodology of characterization is similar, the goal for industry clients is often to understand why a fault occurred and how to prevent it, rather than just achieving an exploit. Laser fault injection offers precise targeting, aiming a 1 micrometer laser spot at specific IPs or cryptographic keys. However, modern process nodes (14nm, 7nm, 3nm) make this increasingly challenging, as a single laser spot can now affect "hundreds of thousands of things on the silicon," making fault localization and repeatability significantly harder.

Challenges of Modern Chip Architectures:

The discussion then shifted to the practical implications of advanced packaging and lithography. Lionel highlighted that package-on-package, chiplet, and 3DIC architectures introduce substantial complexities for physical attackers. Decapping, a prerequisite for laser access, becomes a multi-stage, often dangerous process involving mechanical and chemical methods. Attackers must frequently create custom PCBs to access signals, navigate complex BGA and wire bonding, and characterize signals, adding significant preparation time and specialized tooling requirements. This physical preparation alone can be a "nightmare."

Domenic Forte expanded on 3DIC and chiplets from both offensive and defensive standpoints. He stressed that these architectures inherently expand the attack surface, as chiplets within the same package can become attack vectors against each other. The proximity also reduces the signal-to-noise ratio for both fault injection and side-channel eavesdropping. He cited Intel's Power Via technology as an example: while it integrates power delivery into the silicon, potentially making voltage fault injection easier by direct access, it could also serve as a barrier, complicating chip editing or specific targeting. This duality underscores the "bit of both" nature of these advancements for security.

The Blurring Line: Software-Induced Physical Attacks:

The panel addressed the increasing convergence of software and hardware attacks. Concepts like software-induced physical attacks, clock and voltage manipulation from compromised peripherals, and Rowhammer-class effects were discussed. Domenic highlighted the shift where performance optimizations (e.g., in microarchitectures or 3D integration) are prioritized over security, creating new vulnerabilities. He referenced Chris Fletcher's work on exploiting DVFS (Dynamic Voltage and Frequency Scaling) as a timing side channel, illustrating how software-controlled features can manifest as physical attack vectors without requiring direct physical access. Joe Grand noted that this "remote tier" could even open up attacks to a broader audience who might not have hardware lab expertise but are proficient in software exploitation, leveraging tools like Shodan to find vulnerable connected devices.

Polymorphic Registers: A Defensive Innovation:

Domenic Forte introduced his work on polymorphic registers as a promising defensive primitive. Originating from Jet Propulsion Lab (JPL) in 2002, the initial concept involved circuits that could perform multiple functions and adapt to environmental changes (temperature, voltage). The challenge was their complex design, often requiring evolutionary algorithms. Domenic's colleague at the University of Arkansas developed a technique for manual, predictable control of this polymorphism using voltage.

Domenic applied this to a register design where its first function is normal operation (transparent/hold mode). The key innovation lies in leveraging an otherwise "bad" unused mode: the metastable mode, where data is inherently destroyed. This metastable state becomes the register's second, self-destructive function. If an attacker lowers the voltage by a pre-defined amount (controlled by a specific threshold), the polymorphic register instantly destroys its contents locally, within the register itself, rather than requiring hundreds of cycles for a system-wide self-destruct. This built-in, local, and instant data destruction mechanism requires no additional circuitry. Furthermore, these registers could be configured to force state registers out of a privileged configuration or trigger a reset based on sensed voltage or clock glitches, offering a robust, integrated tamper detection and response. The primary hurdle for this innovation is its lack of demonstration in silicon, with a funding proposal currently pending.

Demo / Proof of Concept

▶ Watch: AI's role as attack accelerant and embedded target (22:00)

While the panel itself did not feature a live demonstration of physical exploitation, the discussion was heavily grounded in real-world attack methodologies and prior proof-of-concept work. Joe Grand, in particular, referenced his extensive experience in performing voltage fault injection and EMFI attacks on commercial devices like Trezor, KeepKey, and RobForm. He detailed the practical steps involved, from using accessible tools like the ChipWhisperer to building custom platforms for precise fault injection campaigns.

Lionel Riviere described the high-end, repeatable fault injection campaigns conducted by eShard, which, while not a public "demo," serve as proof-of-concept for manufacturers to understand vulnerabilities. Domenic Forte's discussion of polymorphic registers highlighted a defensive primitive that, while not yet silicon-proven, has undergone extensive theoretical and simulation-based validation, with the aim of future silicon demonstration. The entire panel served as a meta-demonstration of the feasibility and evolving nature of physical attacks, emphasizing that the tools and techniques are readily available and continuously advancing.

Defensive Implications

▶ Watch: Call to action: Push vendors, demand security, future proof (40:00)

The panel's insights offer crucial guidance for defenders grappling with the escalating threat of physical exploitation. The overarching message is clear: the industry must move beyond reactive security and proactively integrate robust countermeasures.

1. Prioritize and Deploy Defensive Primitives: The most direct implication is the urgent need to integrate advanced defensive primitives into production silicon. Domenic Forte's work on polymorphic registers exemplifies this. These registers, capable of instantly self-destructing data upon detecting voltage anomalies, offer a powerful, localized, and built-in tamper response without additional circuitry. Manufacturers should actively invest in demonstrating such technologies in silicon and making them available as standard IP blocks. Other primitives like voltage tamper detection and self-destructive latches should also be considered foundational elements for any secure chip design.

1. Adopt Systematic Security Engineering Frameworks: The complexity of modern chips and attack vectors necessitates a structured approach to security. Domenic recommended the Cyber Informed Engineering (CIE) framework, developed by the Department of Energy. This 12-principle framework, though focused on critical systems, is highly applicable to complex system-on-chip designs. It provides a systematic methodology for designing, building, and making systems resilient, helping engineers who may not be security experts to integrate security proactively from the ground up, rather than as an afterthought.

1. Demand Accountability from Vendors: A significant barrier to better security is the current market dynamic where manufacturers are not sufficiently pressured to integrate robust defenses. Joe Grand passionately argued that buyers must question vendors, demand proof of security claims, and exert financial pressure by threatening to switch vendors if security is not adequately addressed across all product tiers, not just high-end or certified devices. Lionel Riviere echoed this, noting that manufacturers only prioritize higher security grades when faced with high-stakes assets (e.g., governmental facilities, weapons) or regulatory demands. Insurers, who bear the financial burden of breaches (e.g., crypto wallet hacks), also have a vested interest in demanding better hardware security.

1. Invest in Internal Expertise and Offensive Capabilities: Both Joe and Lionel stressed the importance of hands-on experience. Academia and industry teams should "start playing with the tools that exist" – open-source frameworks, cheap hardware, and accessible fault injection setups. This practical understanding of how chips can be attacked is crucial for designing effective defenses. Manufacturers should allocate budgets for "interesting toys" and dedicated teams to explore attack paths, proving the worth of security investments through internal red-teaming efforts.

1. Anticipate and Mitigate Emerging Threats: Defenders must prepare for remote physical exploitation and the dual role of AI. As the line between software and hardware attacks blurs, understanding how software-induced anomalies can lead to physical vulnerabilities (e.g., Rowhammer, DVFS side channels) is paramount. For AI, while it can accelerate defensive analysis, the immediate concern is securing embedded AI inference models as new assets and understanding how AI can accelerate attacker capabilities. This requires a proactive stance, acknowledging that "security is not one of those things that's being focused on" in the initial rush to deploy new AI capabilities.

Ultimately, the panel concluded that the "deployment gap" is the most critical challenge. The research and solutions exist; the imperative now is for collective action—from engineers, buyers, regulators, and insurers—to demand and implement these defenses at scale.

Key Takeaways

• Democratization of Physical Attacks: Tools and open-source frameworks have made physical exploitation significantly more accessible and affordable, moving it beyond elite labs to a broader "bench tier" of attackers.
• Evolving Attack Surfaces: Advanced chip architectures like 3DIC and chiplets introduce new attack vectors and complexities, while smaller lithography nodes make precise targeting harder but do not eliminate vulnerabilities.
• Remote Physical Exploitation is Emerging: The line between software and hardware attacks is blurring, with potential for software-induced physical effects and hardware implants enabling remote physical attacks.
• AI's Dual Role: AI models embedded in chips are new targets for side-channel attacks, but AI tools (e.g., LLMs) also significantly accelerate attacker capabilities by automating analysis and custom attack path generation.
• Critical "Deployment Gap" in Defenses: Despite decades of research into robust defensive primitives like polymorphic registers and tamper detection, these are largely absent from production silicon due to cost, market pressures, and a lack of demand.
• The Need for Systemic Change: Buyers, regulators, and insurers must exert pressure on manufacturers to integrate security proactively across all product lines, not just high-end devices, and adopt comprehensive security engineering frameworks like Cyber Informed Engineering (CIE).

About the Speaker(s)

• Lionel Riviere: A Security Analyst at eShard, Lionel specializes in high-end physical attacks, particularly laser fault injection. His work focuses on achieving highly repeatable faults and, crucially, understanding the underlying mechanisms of compromise to provide actionable insights for manufacturers to address vulnerabilities. He emphasized the challenges posed by modern lithography and packaging for precise targeting.

• Joe Grand: As a Principal Engineer at Grand Idea Studio, Joe is renowned for his contributions to the democratization of hardware hacking. He has extensively used accessible tools like the ChipWhisperer and built low-cost setups (e.g., using an Amazon CNC router kit for EMFI) to conduct voltage fault injection and EMFI attacks on commercial devices such as Trezor and KeepKey. Joe's work highlights the "bench tier" reality of physical exploitation and the importance of open-source tooling.

• Domenic Forte: A distinguished researcher from the University of Florida, Domenic focuses on developing advanced defensive primitives against physical attacks. His notable contributions include research on polymorphic circuits and self-destructive registers, which aim to provide instant, localized tamper detection and response within silicon. He also provided insights into the security implications of emerging architectures like 3DIC and chiplets from both offensive and defensive perspectives.